ARM Cortex-M Interrupt Priorities

Who gets to interrupt whom.

Cortex-M chips have a nested interrupt controller. Every interrupt has a priority number, and a lower number means more urgent. A higher-priority interrupt can pause a running lower-priority handler.

Give time-critical events, such as a motor fault, the best priority and slow tasks like a button the worst. Keep the number of levels in use small and written down.

Shared data between handlers of different priority needs protection from being changed halfway through a read.